This invention relates to the field of integrated circuits, and more specifically to programmable logic devices.
Programmable Logic Devices (PLDs) are Integrated Circuits (ICs) that are user configurable and capable of implementing digital logic operations. Logic designers typically use PLDs to implement control logic in electronic systems because they are relatively easy to program, and often can be reprogrammed to update the emulated logic function. This often makes the use of PLDs less costly in comparison to custom hardwired or xe2x80x9capplication specificxe2x80x9d integrated circuits (ASICs).
There are several types of PLDS, including Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Devices (CPLDs). FPGAs include configurable logic blocks (CLBs) arranged in rows and columns, IOBs surrounding the CLBs, and programmable interconnect lines that extend between the rows and columns of CLBS. Each CLB includes look-up tables (LUTs) and other configurable circuitry that is programmable to implement a portion of a larger logic function. The CLBs, IOBs and interconnect lines are configured by data stored in a configuration memory of the FPGA. In contrast to the LUT-based CLBs and interconnect lines of FPGAs, CPLDs perform logic using several function blocks that are based on the well-known programmable logic array (PLA) architecture, and utilize a central interconnect matrix to transmit signals between the function blocks. Signals are transmitted into and out of the interconnect switch matrix through input/output blocks (IOBs). However, similar to FPGAs, the input/output function of the IOBs, the logic performed by the function blocks and the signal paths implemented by the interconnect switch matrix are all controlled by configuration data stored in configuration memory of the CPLD.
FIG. 1 is a split-level perspective diagram of a typical CPLD 100. To simplify the following description, CPLD 100 is functionally separated into a logic plane 110, which includes the programmable logic resources (circuits) used to implement selected logic operations, and a configuration plane 150 that includes the configuration memory circuits used to store the configuration data utilized to control the programmable logic resources of logic plane 110. Other simplifications and functional representations are utilized to facilitate the following description.
Referring to the upper portion of FIG. 1, for explanatory purposes, logic plane 110 of CPLD 100 includes features common to XC9500 family of CPLDs that are produced by Xilinx, Inc. of San Jose, Calif. In particular, CPLD 100 includes input/output (I/O) terminals 115, IOBs 120, an interconnect switch matrix 130, and several function blocks (FBs) 140 (one shown). IOBs 120 provide buffering for device input and output signals that are applied to I/O terminals 115. Input signals are passed through IOBs 120 to switch matrix 130, and selected output signals from FB 140 are fed back into switch matrix 130. Each FB 140 includes an AND array 142 that logically ANDs input signals received from switch matrix 130 to form product term (P-term) signals that are applied to any of several macrocells 145. Each macrocell 145 is programmable to generate a sum-of-products term using selected P-term signals. These sum-of-products terms are output from macrocells 145 to IOB 120 (along with optional corresponding output enable signals). Those of ordinary skill in the art generally understand these and other circuits and operations of the programmable circuitry of logic plane 110 (described above).
Referring to the lower portion of FIG. 1, configuration plane 150 generally includes a configuration circuit 160, a non-volatile memory array 170, and a volatile memory array 180. Configuration circuit 160 performs several functions associated with configuration plane 150, including configuration operations during which configuration data is transferred from non-volatile memory array 170 to volatile memory array 180. Non-volatile (e.g., flash) memory array 170 is provided to persistently store the configuration data that is transferred to volatile memory array 180 during a configuration operation typically performed at device power-up. Volatile memory array 180 includes volatile (e.g., SRAM) configuration memory cells 182 arranged in rows and columns that temporarily store configuration data (e.g., until power to CPLD 100 is terminated). During a configuration operation, configuration circuit 160 routes configuration data from non-volatile memory array 170 to corresponding configuration memory cells 182 of volatile memory array 180. During subsequent xe2x80x9cnormalxe2x80x9d operation of CPLD 100, the configuration data stored in volatile memory array 180 is used to control associated programmable logic resources of logic plane 110 via connections 185 (indicated by dashed lines with arrows) in a manner understood by those of ordinary skill in the art, thereby causing CPLD 100 to implement the logic operation defined by the configuration data.
FIG. 2 is a simplified circuit diagram showing portions of CPLD 100 in additional detail. In particular, FIG. 2 shows a simplified representation of FB 140, IOB 120, and configuration memory array (CONF MEM ARRAY) 180.
Referring to the upper left portion of FIG. 2, the illustrated portion of FB 140 includes a portion of logic AND array (andA) 142, which is depicted as logic AND gates 143 that generate product terms (P-terms) on macrocell input lines 144, and a portion of a macrocell 145 depicted as including a logic OR gate 147, a flip-flop (FF) 148, and an output enable (OE) buffer 149. Logic OR gate 147 typically receives several P-terms from logic AND array 142, and generates a sum-of-products (SOP) term that is optionally stored in FF 148 and transmitted to an associated IOB 120. Similarly, OE buffer 149 receives an associate P-term from logic AND array 142, and transmits the P-term to IOB 120.
Referring to the upper right portion of FIG. 2, IOB 120 includes an input buffer 121, an output driver circuit 123, an output enable (OE) multiplexer 125, a slew-rate control (SRC) circuit 127, and a user-programmable ground (UPG) circuit 129. Input buffer 121 detects and buffers input signals applied to I/O terminal 115 from external devices. Output driver circuit 123 receives the sum-of-products (SOP) term transmitted from macrocell 145, an output enable (OE) signal from OE multiplexer 125, and generates an output signal on I/O terminal 115. OE multiplexer 125 has input terminals respectively connected to receive the P-term transmitted from OE buffer 149, a global OE control signal, a fixed OE enable (xe2x80x9c1xe2x80x9d), and a fixed OE disable (xe2x80x9c0xe2x80x9d). OE multiplexer 125 selectively passes one of these OE signals to the OE terminal of output driver 123 in response to data stored configuration memory array 180 (e.g., in associated configuration data cells 182-1 and 182-2). SRC circuit 127 controls the slew rate of the output signals generated by output driver 123 in accordance with configuration data stored in configuration memory array 180 (e.g., in associated configuration data cell 182-3). Finally, when a particular I/O terminal 115 is not utilized in a user""s logic operations, UPG circuit 129 allows the user to selectively tie the I/O terminal 115 to ground in accordance with configuration data stored in memory cell 182-4. Other circuitry of IOB 120 and associated connections to configuration memory array 180 are omitted for brevity.
Power control (conservation) is increasingly important in many modern platforms, and particularly in battery powered devices (e.g., laptop computers and personal digital assistants). Power control is typically performed by monitoring the activity in the system, and terminating the power supply provided to idle IC devices of the system.
PLDs, such as PLD 100 (see FIGS. 1 and 2), are often used in combination with power control devices to perform power control functions in electronic systems. Typically, a portion of the programmable logic circuitry of the PLD is programmed to monitor the activity of the various devices in a system, and to generate control signals that are used to reduce or terminate the power provided to certain IC devices of the system. The power control signals generated by the PLD are transmitted to a power control device, which is a device including high current transistors that selectively apply or terminate the flow of power to selected IC devices of the system. An example of one such system is provided below.
FIG. 3 illustrates an exemplary system 200 in which PLD 100 is used in combination with a conventional power control device 210 to control the power consumed by system 200. In this example, the system includes PLD 100 (described above), a memory device (SRAM) 220-1, and a central processing unit (CPU) 220-2 that communicate using a system bus 205.
Power control device 210 (e.g., a Quad Power Supply Controller, model number SMT4004, produced by Summit Microelectronics, Inc. of Campbell, California) includes input terminals 212-IN1 and 212-IN2 that are connected to respective IOBs of PLD 100 (e.g., IOB 120 shown in FIG. 2), and also includes a first output terminal 212-OUT1 that is connected to the power (VCC) pin of SRAM 220-1, and a second output terminal 212-OUT2 that is connected to the power (VCC) pin of CPU 220-2.
Power control device 210 acts as a switch that controls the supply of power to SRAM 220-1 and CPU-220-2 in response to control signals generated by PLD 100. In particular, a portion of the programmable logic circuitry of PLD 100 is configured to implement power control logic (e.g., to recognize idle periods during which SRAM 220-1 and/or CPU 220-2 can be powered down). When such an idle period is detected, PLD 100 generates power control signals on one or both of input terminals 212-IN1 and 212-IN2.
FIG. 4 is a simplified circuit diagram showing a portion of system 200 in additional detail. In particular, FIG. 4 shows portions of PLD 100 that are connected to input terminal 212-IN2 of power control device (PCD) 210, and shows a portion of PCD 210 that is used to control CPU 220-2. Circuitry similar to that shown in FIG. 4 is also used to control SRAM 220-1 (shown in FIG. 3).
Referring to FIG. 4, a simplified output driver circuit 123 of IOB 120 includes a buffer 123-1 and a CMOS switch 123-2. The output terminal of buffer 123-2 is connected to the gate terminals of the n-channel (N) and p-channel (P) transistors of CMOS switch 123-2. An output terminal of CMOS switch 123-2 is connected to I/O terminal 115, which in turn is connected by a conductor to input terminal (pad) 212-IN2 of PCD 210. PCD 210 includes high current transistor 215, which is connected between VCC and output terminal (pad) 212-OUT2, and is sized to transmit sufficient current to power CPU 220-2. Output terminal 212-OUT2 is connected by a conductor to input terminal (pad) 225 of CPU 220-2.
During operation of system 200, FB 140 of PLD 100 monitors various signals indicating system activity, and generates a sum-of-products data signal in accordance with the implemented power control logic. During normal operation of system 200, buffer 123-1 receives a low voltage data signal from a macrocell of FB 140, and passes the low voltage data signal to CMOS switch 123-2. The low voltage data signal turns on p-channel transistor P, thereby pulling I/O terminal 115 to VCCIO. The resulting high voltage on I/O terminal 115 is transmitted to input terminal 212-IN2 of PCD 210, thereby turning on high current transistor 215, which in turn passes the resulting high (VCC) power signal to input terminal 225 of CPU 220-2. Subsequently, when the power control logic implemented by PLD 100 determines that CPU 220-2 can be powered down, tri-state buffer 123-1 receives a high voltage data signal from a macrocell of FB 140, and passes the high voltage data signal to CMOS switch 123-2. The high voltage data signal turns on n-channel transistor N, thereby pulling down I/O terminal 115 to ground. The resulting low voltage on I/O terminal 115 is transmitted to input terminal 212-IN2 of PCD 210, thereby turning off high current transistor 215, which in turn terminates the power supplied to CPU 220-2.
The total cost of an electronic system is largely determined by the components (ICs) that make up the system. Generally speaking, when the function of a discrete component in a system can be performed by other components in a system, then the overall cost of the system can be reduced by eliminating that component. For example, most of the cost of system 200 (FIG. 3) is determined by the individual costs of PLD 100, PCD 210, SRAM 220-1, and CPU 220-2. If the function of PCD 210 can be performed by PLD 100, then elimination of PCD 210 typically would significantly reduce the cost of system 200.
A problem with eliminating PCD 210 from system 200 is that power control requires the use of a high current transistor, such as high current transistor 215 (shown in FIG. 4). That is, CMOS switch 123-2 of IOB 120 typically lacks the capacity to provide a high current (e.g., 200 milliamperes) that is typically required to power an IC. Further, simply increasing the size of CMOS switch 123-2 to provide this current capacity is undesirable because: a) not all devices connected to each IOB require (or can handle) a high current signal; b) the amount of space needed to produce a CMOS switch of this size would take up valuable chip area; and c) such a modification would produce additional capacitance and a slower slew rate.
Accordingly, what is needed is a power control output circuit for use in the IOBs of a PLD that can be selectively activated to generate a high current output signal sufficient to drive an IC device. What is also needed is a PLD having one or more IOBs incorporating such a power control output circuit.
The present invention is directed to a power control output circuit for a PLD that allows the PLD to selectively operate in either a low current (xe2x80x9cnormalxe2x80x9d) output mode, or a high current power control mode. In one embodiment, the power control output circuit is incorporated into one or more Power Control Input/Output Blocks (PC-IOB) provided on the PLD. In the low current output mode, the high current output circuit is deactivated, and the PC-IOB operates essentially the same as a conventional IOB (e.g., relatively low current output signals are transmitted to a device I/O terminal using a conventional CMOS switch). In the high current power control mode, the high current output circuit turns on a high current transistor in response to data output signals, thereby generating high current power control output signals at the device I/O terminal. This high current power control output signal can be supplied to the power (VCC) terminal of an IC device included in the system incorporating the PLD.
In accordance with an embodiment of the present invention, a power control output circuit includes an output driver that generates relatively low current output signals on a device terminal during xe2x80x9cnormalxe2x80x9d (low current) operating modes, and a high current output circuit that generates relatively high current output signals on a device terminal during power control operating modes. The output driver includes a buffer having an input terminal connected to receive data output signals, and an output terminal connected to the input terminal of a CMOS switch, which has an output terminal connected to the device I/O terminal. The high current output circuit includes a high current (power control) transistor and a switch (e.g., a multiplexer). The high current transistor is connected between a high voltage source (VCCIO) and the device I/O terminal, and is controlled by a signal passed from the output driver by the switch. In one A marked-up copy of the specification is provided herewith in the attached appendix. embodiment, the high current transistor is a p-channel transistor, and the; multiplexer having a first input terminal connected to the high voltage source, a second input terminal connected to receive the buffered output signal generated by the buffer, and an output terminal connected to the gate terminal of the power control transistor. In another embodiment, the high current transistor is an n-channel transistor, and one input terminal of the multiplexer is connected to a low voltage source (e.g., VSS or ground), a second input terminal connected to the output driver, and the multiplexer output terminal is connected to the gate terminal of the power control transistor. A select terminal of the multiplexer in each embodiment is controlled in accordance with a desired operating mode. During the xe2x80x9cnormalxe2x80x9d (i.e., low current) operating mode, the multiplexer maintains the power control transistor in a turned-off (non-conducting) state such that only the low current output signal from the output driver is transmitted to the device I/O terminal. During the power control mode, the multiplexer passes a data output signal from the output driver to the gate terminal of the power control transistor, thereby selectively turning on the power control transistor each time the data output signal is logic xe2x80x9c0xe2x80x9d (or xe2x80x9c1xe2x80x9d) Accordingly, a high current (power control) output signal is selectively generated at the device I/O terminal that can be used to power selected IC devices of a system without requiring a discrete power control device, thereby reducing the total cost of the system.
In another embodiment of the present invention, a programmable logic device (PLD) includes one or more power control IOBs (PC-IOBs), a configuration memory array, and programmable logic circuitry for implementing a system logic operation in accordance with configuration data stored in the configuration memory array. Each PC-IOB including the power control output circuit (described above) in which the switch (e.g., the select terminal of the two-input multiplexer) is controlled using a power control configuration memory cell of the configuration memory array. Accordingly, during xe2x80x9cnormalxe2x80x9d operations (i.e., when power control functions are not desired), a user programs the power control configuration memory cells to maintain the power control transistors of the one or more PC-IOBs in a turned-off (non-conducting) state-such that only low current output signals are generated at the device I/O terminals. Conversely, when power control is desired, a user programs a portion of the programmable logic circuitry to perform the desired power control function such that a power control signal is routed to the one or more PC-IOBs, and programs the power control configuration memory cell to connect the output driver of the PC-IOB to the gate terminal of the power control transistor. Subsequently, when a power control data output signal is generated by the portion of the programmable logic circuitry performing the power control function, the power control transistor is turned on to generate a high current output signal at the device terminal. Accordingly, a PLD incorporating one or more power control output circuits in accordance with the present invention reduces system costs by providing power control functions without increasing the number of discrete components needed to produce the system.